1. Field
The present disclosure relates generally to translation lookaside buffers, and more specifically, to methods and systems for optimizing translation lookaside buffer entries.
2. Background
Many existing computer systems today utilize virtual memory. Virtual memory is a technique that abstracts memory into a large, uniform array of virtual storage, which exceeds memory readily available to the processor. This separation allows a large virtual memory to be provided for programmers when only a smaller physical memory, commonly a semiconductor memory (such as but not limited to RAM or DRAM) hereinafter referred to simply as “memory”, is available, thereby freeing programmers from concern over memory storage limitations. As a result, numerous applications can be launched by loading portions of them from higher latency hard drive storage to lower latency memory even though the lower latency memory is not large enough to hold them all. This may be achieved by identifying portions of memory that have not been used recently and copying them back onto the hard drive. This frees up space in memory to load new portions of memory for more immediate use.
In many processing systems today, a central processing unit (CPU) uses virtual memory to execute programs. In such processing systems a virtual address is mapped to a corresponding physical address. Typically, this mapping is performed by a translation lookaside buffer (“TLB”), which is nothing more than a memory that maps the most often used virtual memory page addresses to their corresponding physical memory page addresses.
Commonly, each TLB entry maps one page in memory to a virtual memory page address. This limits the number of addresses that can be represented by each TLB entry. Since maintaining a TLB requires system resources, it would be desirable to provide more efficient methods and systems for optimizing TLB entries by consolidating multiple contiguous page entries into a single entry.